1. Field of the Invention
The present invention relates to semiconductor devices and fabrication methods thereof. In particular, the invention relates to semiconductor devices formed on an SOI (Silicon on Insulator) substrate and fabrication methods thereof. Also, the invention relates to bipolar transistors having a control electrode formed via an insulating film on a base region.
2. Related Background Art
In the development of an advanced information society, there has been a great contribution of improved technology for semiconductor devices such as transistors. Among such devices is included a vertical bipolar transistor such as a planar bipolar transistor. The vertical bipolar transistor operates at high speed as a single element, and can act effectively for current amplification and switching. However, when incorporated as an element to an integrated circuit, the vertical bipolar transistor is difficult to combine with a condenser (capacitor) or other transistor resulting from the problem of the process times. One method of constituting an integrated circuit by the combination of a bipolar transistor with other elements is to laterally arrange the bipolar transistor to enhance coordination with the process times. There is a Bi-CMOS structure in which a MOS transistor is chose as another element to combine with the bipolar transistor. Bi-CMOS allows for the design of logic with high speed and low consumption power, because the bipolar transistor operating at high speed and the MOS transistor operating at high speed and the MOS transistor operating at low consumption power can be incorporated into one IC.
The process of incorporating the bipolar transistor as one element in an IC of a Bi-CMOS fabricated on a silicon wafer is referred to as a silicon wafer bulk process. Conventionally, the vertical bipolar transistor and the lateral bipolar transistor has been formed through the silicon wafer bulk process, as shown in FIGS. 67 and 68.
In FIG. 67, and NPN-type vertical bipolar transistor 301 is electrically separated from other elements by an element separation region 302. Herein, 303 is a P-type silicon substrate, 304 is an N.sup.+ -type region which is a collector region for the vertical bipolar transistor 301, 305 is an N.sup.- -type epitaxial region, 306is a collector lead-out layer, 307 is a P-type region for element separation, 308 is a selective oxidation region, 309 is a P-type base region, 310 is an N.sup.+ -type emitter region, 311 is an interlayer insulating layer, 312, 313, and 314 are Al electrodes, and 315 is a passivation insulating layer.
In FIG. 68, a PNP-type lateral bipolar transistor is shown. The PNP-type lateral bipolar transistor 321 is electrically separated from other elements by an element separation region 322. Herein, 323 is a P-type silicon substrate, 324 is an N.sup.+ -type region which is a base region for the lateral bipolar transistor 321, 325 is an N.sup.- -type epitaxial region, 326 is a base lead-out layer, 327 is a P-type region for element separation, 328 is a selective oxidation region, 329 is a P.sup.+ -type emitter region, 330 is an P.sup.+ -type collector region, 331 is an interlayer insulating layer, 332, 333, and 334 and AI electrodes, and 335 is a passivation insulating layer.
In the silicon waver bulk process, if the element separation region for separation the transistor from other elements is not provided as above described, some elements bring about latch-up or a parasitic transistor is produced. Or even if the element separation region is provided, the element separation may not be successful. For these reasons, ICs sometimes malfunction and become inoperable due to the design.
In practice, a Bi-CMOS is used for a decoder unit such as a DRAM, and has a structure as illustrated in FIGS. 69A and 69B. However, when this Bi-CMOS is formed of bulk silicon, the process becomes extremely complex because when fabricating a CMOS and a vertical bipolar transistor, element separation must be performed. Therefore, the yield is reduced and the cost is increased. If the lateral bipolar transistor is fabricated in bulk, the process times may be decreased, but the element separation region must be made. To resolve this problem, numerous research has been performed for forming Bi-CMOS on the SOI substrate. The fabrication of Bi-CMOS using the SOI substrate. The fabrication of Bi-CMOS using the SOI substrate allows the dielectric separation between elements to be made simpler. When fabricating a bipolar transistor using the SOI substrate, the lateral bipolar transistor may be fabricated in a smaller number of process times. The lateral bipolar transistor may be inferior in performance to the vertical bipolar transistor, but can be fabricated through a fabricating process which is also used for the CMOS fabrication. Further, since the lateral bipolar transistor is fabricated on the SOI structure, it can eliminate any external base between emitter and base which will cause a degradation of current amplification gain (h.sub.FE) SO that its characteristics can be improved.
The method of forming a MOS transistor on the SOI substrate is suitable from the respects of suppressing the short channel effect and making the microstructure of an element. For the above reasons, the method of forming Bi-CMOS having lateral bipolar transistor on the SOI substrate is expected to be promising.
In fabricating Bi-CMOS on the SOI substrate, the lower voltage is required from a point of withstanding voltage and consumption of power of an element for the microstructure of necessary elements. However, in the bipolar transistor, the potential V.sub.BE between emitter and base is not zero volts, and may be about 0.6 to 0.7 volts at minimum. Consequently in a circuit producing waveforms as shown in FIG. 70, the amplitude of a signal transferred is reduced 1.2 to 1.4 volts from the power source voltage of 3.3 volts, and it is necessary that the effective voltage for driving is 1.9 to 2.1 volts. That it, the on-state voltage of a bipolar transistor is about 0.7V while the on-state voltage of a MOS transistor is about 0.3 to 0.4V.
For such reasons, there is a problem that the driving power for a Bi-CMOS is extremely degraded at low voltages, for which it is the only way in the state of the art to construct a Bi-CMOS with the MOS circuit when the lower voltage ICs for use with portable commodities are made or the reduction of power voltage due to a microstructure is obliged. The construction only with the MOS circuit may not allow the high speed IC to be fabricated.
According to the present invention one method proposed for resolving this problem is one in which a bipolar transistor provided with a control electrode on the base region (hereinafter referred to as a bipolar transistor with control electrode) is used to reduce the on-state voltage equivalent to that of the MOS transistor. This transistor can provide an on-state current with a large threshold for the on-state voltage by applying a voltage to the control electrode to adjust the base region to be in a weak inversion state (the p-type base region becomes i-type for the NPN transistor).
FIG. 71 shows a structure of the bipolar transistor with control electrode. In FIG. 71, 501 is an oxide film, 502 is a collector, 503 is a base, 504 is an emitter, 505 is a collector, 503 is a base, 504 is an emitter, 505 is an oxide film (insulating film), 506 is a control electrode, 507 is in interlayer insulating film, and 508 is a metal electrode.
FIG. 72 shows a gammel plot diagram of the bipolar transistor with control electrode. In FIG. 72, the solid line indicates the characteristic of the bipolar transistor with control electrode, and the dashed line indicates the characteristic of a conventional bipolar transistor. The axis of ordinates indicates the base current (I.sub.B) and the collector current (I O), and the axis of abscissas indicates the base voltage. Supposing that the on-state current occurs when the collector current (I.sub.0) flows at 1 .mu.A, it will be found that the on-state voltage of a conventional bipolar transistor not having control electrode is about 0.7V while that of the bipolar transistor with control electrode is smaller, such as about 0.4V. That is, the lateral bipolar transistor with control electrode can generate a equal on-state current with smaller on-state voltage than the bipolar transistor having no control electrode.
On the other hand, it is desired that the bipolar transistor with control electrode may be operated at a higher speed. However, since the transistor of FIG. 71 is of the lateral type, the base width (t.sub.m in FIG. 71) is of the lateral type, the base width (t.sub.m in FIG. 71) significantly affecting the high speed characteristic may be determined by a photolithography technique. In the state of the art, the base width becomes about 0.5 .mu.m at a minimum, making it difficult to fabricate the high speed transistor. Hence, according to the present invention a fabrication method is devised for reducing the base width of the bipolar transistor with control electrode.
Also, the bipolar transistor with control electrode as shown in FIG. 71 must control the voltage between the control electrode and the base region so that the base region may be in a weak inversion state, and always maintain its voltage during operation. Therefore, according to the present invention a semiconductor device has been devised which needs no application of voltage between the control electrode for the bipolar transistor with control electrode and the base region.